Self-shadowing MEM structures

ABSTRACT

Self-shadowed microelectromechanical structures such as self-shadowed bond pads, fuses and compliant members and a method of fabricating self-shadowing microelectromechanical structures that anticipate and accommodate blanket metalization process steps are disclosed. In one embodiment, a self-shadowed bond pad ( 10 ) configured for shadowing an exposed end ( 44 A) of a shielded interconnect line ( 44 ) connected to the bond pad ( 10 ) from undesired metalization during a metalization fabrication process step includes electrically connected overlaying first, second and third bond pad areas ( 42, 72, 92 ) patterned from respective first, second and third layers ( 40, 70, 90 ) of material deposited on a substrate ( 20 ). The exposed end ( 44 A) of the interconnect line ( 44 ) abuts an edge of the first bond pad area ( 42 ). The third bond pad area ( 92 ) includes at least one tab portion ( 94 ) extending laterally from an edge of the third bond pad area ( 92 ) to shadow an area on the substrate ( 20 ) including the exposed end ( 44 A) of the interconnect line ( 44 ) abutting the edge of the first bond pad area ( 42 ).

FIELD OF THE INVENTION

The present invention relates generally to microelectromechanicalsystems (MEMS), and more particularly to the design and fabrication ofbond pads, fuses, compliant members and other MEMS structures portionsof which preferably remain non-metalized.

BACKGROUND OF THE INVENTION

MEMS can include numerous electromechanical devices fabricated on asingle substrate, many of which are to be separately actuated in orderto achieve a desired operation. For example, a MEMS optical switch mayinclude numerous mirrors that are each positionable in a desiredorientation for reflecting optical signals between originating andtarget locations upon actuation of one or more microactuators associatedwith each mirror. In order for each mirror to be separately positioned,separate control signals need to be supplied to the microactuatorsassociated with each mirror. One manner of accomplishing this is toconnect each microactuator to a control signal source with a separateelectrical conductor (i.e., an interconnect line) fabricated on thesurface of the substrate that extends between its associatedmicroactuator and a bond pad at the periphery of the substrate where itcan be easily connected to an off-chip control signal source. In thisregard, since there are numerous interconnect lines, there are typicallynumerous bond pads arranged in close proximity to each other along theperiphery of the substrate.

In fabricating the multiple bond pads it may be desirable to employ ablanket metalization process step wherein the entire region of thesubstrate where the bond pads are located is covered with gold oranother highly conductive material rather than trying to employ a shadowmask that restricts application of the metal to only the surfaces of theindividual bond pads. However, such blanket metalization has thedrawback that it may lead to short circuit conditions. For example, ifthe interconnect lines are electrically isolated from each other byoverlying shield structures, the shield structures cannot contact thebond pads and thus must end prior to the bond pads thereby exposing theinterconnect lines for a short distance in the gaps between the bondpads and the ends of the shield structures. Thus, if blanketmetalization is employed, the exposed portions of the interconnect linesmay receive undesired metalization leading to short circuits betweenindividual interconnect lines and their associated shield structures orbetween adjacent interconnect lines. Furthermore, even if blanketmetalization is not employed, slight misalignment of an appropriatelyconfigured shadow mask can also result in undesired metalization of theexposed portions of the interconnect lines.

SUMMARY OF THE INVENTION

Accordingly, the present invention provides self-shadowedmicroelectromechanical structures such as self-shadowed bond pads, fusesand compliant members (e.g., springs) and a method of fabricatingself-shadowing microelectromechanical structures that anticipate andaccommodate blanket metalization process steps. In accordance with thepresent invention, microelectromechanical structures are designed toincorporate upper level projections (e.g.. tabs, cantilevered edges, orthe like) that extend laterally outward from upper levels of thestructures to shadow an area on the substrate including exposed lowerlevel structures (e.g., ends of interconnect lines, fuse filaments orthe like) that are to remain non-metalized. Thus, in accordance with thepresent invention, the necessary shadow masks are, in effect,incorporated directly into the structures that are fabricated thusallowing for blanket metalization and reducing the likelihood of errantmetalization even when shadow masks are used in the metalizationprocess.

According to one aspect of the present invention, a self-shadowedmicroelectromechanical structure configured for shadowing a portionthereof from undesired metalization during a metalization fabricationprocess step includes a lower layer of material deposited on asubstrate. The lower layer of material may comprise an electricallyconductive material, depending upon the requirements of the structuresthat are to be formed therefrom. In this regard, the substrate may becomprised of silicon covered by a dielectric stack (e.g., a lower layerof silicon oxide and upper layer of silicon nitride) and theelectrically conductive material may comprise polysilicon doped with anappropriate material (e.g., phosphorous) to make it electricallyconductive. A lower structure is patterned from the lower layer ofmaterial. The lower structure includes at least a portion that is toremain non-metalized. An upper layer of material is also deposited onthe substrate. The upper layer of material may comprise an electricallyconductive material (e.g., doped polysilicon), depending upon therequirements of the structures that are to be formed therefrom. Theremay be one or more intervening layers of sacrificial material (e.g.,silicon oxide or silicate glass) and/or non-sacrificial material (e.g.,additional doped polysilicon layers) between the lower and upper layersof electrically conductive material. Further, there may be one or morepreviously deposited layers (e.g., sacrificial material and/ornon-sacrificial material) between the lower layer of material and thesubstrate. An upper structure is patterned from the upper layer ofmaterial. The upper structure includes a laterally extending portionthereof that extends laterally from the upper structure to shadow anarea on the substrate that is outside of the main area occupied by theupper structure and that includes the portion of the lower structurethat is to remain non-metalized. By way of example, the lower stricturemay comprise a shielded interconnect line having an exposed portion thatis to remain non-metalized and the upper structure may comprise a bondpad area. In one embodiment, the laterally extending portion of the bondpad area comprises a tab extending laterally from an edge of the bondpad area to shadow the exposed portion of the interconnect line andalso, preferably, a small area around the exposed portion of theinterconnect line. In another embodiment, the entire edge of the bondpad area is cantilevered outward to shadow the exposed portion of theinterconnect line and also a larger additional area adjacent to the bondpad area. By way of another example, the lower structure comprises aninterconnect line having an exposed portion that is to remainnon-metalized and the upper structure comprises a tab extendinglaterally to shadow the exposed portion of the interconnect line from apost extending upward from a shield structure overlying the interconnectline. By way of further example, the upper structure may comprise apositionable mirror and the lower electrically conductive structure maycomprise at least one filament for holding the mirror in place until thefilament is severed or at least one compliant member (e.g., a spring)connecting the mirror to other MEM structures (e.g., an actuator arm).In one embodiment, the laterally extending portion of the mirrorcomprises a tab extending laterally from an edge of the mirror to shadowthe filament or compliant member and also, preferably, a small areaaround the filament or compliant member. In another embodiment theentire edge of the minor is cantilevered outward to shadow the filamentor compliant member and also a larger additional area adjacent to themirror.

According to another aspect of the present invention, a method forself-shadowing a portion of a microelectromechanical structurefabricated on a substrate from undesired metalization during ametalization fabrication process step begins with depositing a lowerlayer of material on a substrate (e.g., a silicon substrate have adielectric stack deposited thereon). Depending upon the requirements ofthe structures that are to be formed from the lower layer of material,the lower layer of material may be an electrically conductive material(e.g., doped polysilicon). A lower structure (e.g., an interconnectline, a filament, or a compliant member) is then patterned from thelower layer of material. An upper layer of material is then deposited onthe substrate. Depending upon the requirements of the structures thatare to be formed from the lower layer of material, the lower layer ofmaterial may be an electrically conductive material (e.g., dopedpolysilicon). One or more intervening layers of sacrificial material(e.g., silicon oxide or silicate glass) and/or non-sacrificial material(e.g., additional doped polysilicon layers) may be deposited and removedand/or patterned between deposition of the lower and upper layers ofmaterial. Further, the lower layer of material may be the first layer ofmaterial deposited on the substrate, or it may be deposited over one ormore previously deposited layers (e.g., sacrificial material and/ornon-sacrificial material). An upper structure (e.g. a bond pad area, amoveable mirror, or a post extending upward from a shield structure overan interconnect line) is patterned from the upper layer of material. Inthis regard, the upper structure is patterned to include a laterallyextending portion thereof (e.g., a tab or a cantilevered edge) thatextends laterally from the upper structure to shadow an area on thesubstrate outside of the main area occupied by the upper structure andincluding the portion of the lower structure that is to remainnon-metalized.

According to a further aspect of the present invention, a self-shadowingbond pad configured for shadowing an exposed end of a shieldedinterconnect line connected to the bond pad from undesired metalizationduring a metalization fabrication process step includes a first bond padarea formed in a first layer of electrically conductive material (e.g.,doped polysilicon) deposited on a substrate. In this regard, the exposedend of the interconnect line abuts an edge of the first bond pad area.At least one wall is formed in a second layer of electrically conductivematerial deposited on the substrate that extends upward from the firstbond pad area. In one embodiment, the first bond pad area is rectangularand there are four walls extending upward from the first bond pad areaadjacent to the perimeter of the first bond pad area. A second bond padarea is formed in the second layer of electrically conductive material.The second bond pad area is supported by the wall(s) formed in thesecond layer of electrically conductive material in an overlayingrelationship above the first bond pad area. In one embodiment, thesecond layer of electrically conductive material is comprised of athinner lower layer of doped polysilicon and a thicker upper layer ofdoped polysilicon. At least one wall is formed in a third layer ofelectrically conductive material that extends upward from the secondbond pad area. In one embodiment, the second bond pad area isrectangular and there are four walls extending upward from the secondbond pad area adjacent to the perimeter of the second bond pad area. Athird bond pad area is formed in the third layer of electricallyconductive material. The third bond pad area is supported by wall(s)formed in the third layer of electrically conductive material in anoverlaying relationship above the second bond pad area. The third bondpad area includes at least one tab portion extending laterally from anedge of the third bond pad area to shadow an area on the substrateincluding the exposed end of the interconnect line abutting the edge ofthe first bond pad area. The rigidity of the first, second and thirdbond pad areas may be enhanced by having layers of dielectric material(e.g., silicon oxide or silicate glass) between the first bond pad areaand the substrate, between the first bond pad area and the second bondpad area and between the second bond pad area and the third bond padarea. The self-shadowed bond pad may also include at least one wallformed in a fourth layer of electrically conductive material depositedon the substrate that extends upward from the third bond pad area. Inone embodiment, the third bond pad area is rectangular and there arefour walls extending upward from the third bond pad area adjacent to theperimeter of the third bond pad area. A fourth bond pad area is formedin the fourth layer of electrically conductive material and is supportedby the wall(s) extending upward from the third bond pad area in anoverlaying relationship above the third bond pad area. The fourth bondpad area includes at least one tab portion extending laterally from anedge of the fourth bond pad area over the tab portion extending from theedge of the third bond pad area. The rigidity of the tab portions of thethird and fourth bond pad areas can be enhanced by fabricating a postthat extends vertically between the tab portions. The rigidity of thefourth bond pad area may be enhanced by including a layer of dielectricmaterial (e.g., silicon oxide or silicate glass) between the third andfourth bond pad areas.

According to one more aspect of the present invention, a self-shadowedmicroelectromechanical fuse structure for temporarily holding a moveablemicroelectromechanical structure in place while remaining non-metalizedduring a metalization fabrication process step includes lower and upperlayers of material deposited on a substrate. The lower and upper layersof material may be electrically conductive material (e.g., dopedpolysilicon), depending upon the requirements of the structures formedtherefrom. There may be one or more intervening layers of sacrificialmaterial (e.g., silicon oxide or silicate glass) and/or non-sacrificialmaterial (e.g., additional doped polysilicon layers) between the lowerand upper layers of material. Further, there may be one or morepreviously deposited layers (e.g., sacrificial material and/ornon-sacrificial material) between the lower layer of material and thesubstrate. The moveable microelectromechanical structure is patternedfrom both the lower and upper layers of material. At least one filament,and preferably multiple filaments, are patterned from the lower layer ofmaterial. The filament(s) are connected to the lower layer of themoveable microelectromechanical structure to temporarily hold themoveable microelectromechanical structure in place. The filament(s) maybe severed (e.g., by application of a sufficient electrical currenttherethrough) to free the moveable microelectromechanical structure fordesired movement. At least one tab (and possibly multiple tabs wherethere are multiple filaments distributed around the perimeter of themoveable structure), is patterned from the upper layer. The tab issupported over an area on the substrate including the filament tothereby shadow the filament during metalization of the moveablestructure. In one embodiment, the tab extends laterally from an edge ofthe upper layer of the moveable microelectromechanical structure. Inanother embodiment, the tab extends laterally from an upper layerportion of a bond pad structure that is fixed to the substrate.

These and other aspects and advantages of the present invention will beapparent upon review of the following Detailed Description when taken inconjunction with the accompanying figures.

DESCRIPTION OF THE DRAWINGS

For a more complete understanding of the present invention and furtheradvantages thereof, reference is now made to the following DetailedDescription, taken in conjunction with the drawings, in which:

FIGS. 1A-G are perspective views illustrating the microfabricationprocess of one embodiment of a self-shadowed bond pad in accordance withthe present invention:

FIGS. 2A-G are top views illustrating enlarged portions of theself-shadowed bond pad shown in FIGS. 1A-G;

FIG. 3 is a cross-sectional view of the self-shadowed bond pad takenalong line A--A in FIG. 1G;

FIG. 4 is a perspective view of another embodiment of a self-shadowedbond pad in accordance with the present invention;

FIG. 5 is a perspective view of a further embodiment of a self-shadowedbond pad in accordance with the present invention; and

FIGS. 6A-B are perspective views showing one embodiment of a MEM mirrorthat is temporarily held in place by a plurality of non-shadowedfilaments arranged around the periphery of the MEM mirror;

FIG. 6C is a perspective view of a portion of one embodiment of a MEMmirror configured to shadow the filaments in accordance with the presentinvention;

FIG. 7A is a perspective view showing a portion of one embodiment of aMEM mirror having a non-shadowed compliant member extending from an edgethereof; and

FIG. 7B is a perspective view of a portion of one embodiment of a MEMmirror configured to shadow the compliant member in accordance with thepresent invention.

DETAILED DESCRIPTION

In the description that follows, it should be noted that in the figuresdescribed herein, the various polysilicon and sacrificial layers andstructures shown are idealized representations of the actual layers andstructures that are formed in the various processing steps. In thisregard, the comers of various structures may be somewhat rounded asopposed to square as is depicted, and polysilicon layers of materialoverlying sacrificial layers may, for example, have depressionscoinciding with the locations of cuts made in the sacrificial layersinstead of being perfectly level across the cuts. The size of thedepressions and other defects, if any, may be reduced through the use ofintermediate chemical mechanical polishing steps to planarize thevarious layers of polysilicon and sacrificial material after they aredeposited.

Referring to FIGS. 1A-G, FIGS. 2A-G, and FIG. 3 there are shownperspective and top views, respectively, illustrating themicrofabrication process of one embodiment of a self-shadowed bond pad10. Although described in the context of the interface between aninterconnect line and a bond pad, it will be appreciated that theself-shadowing concept herein described may generally be incorporatedinto many different electrical and non-electrical MEM structures. Themicrofabrication process begins with a substrate 20 having a firstdielectric layer 30 formed thereon. In this regard, the substrate 20 maybe comprised of silicon, and the first dielectric layer 30 may becomprised of a lower layer 30A of thermal oxide (e.g., typically about630 nanometers thick) formed by a wet oxidation process at an elevatedtemperature (e.g., 1050° C. for about 1.5 hours) and an upper layer 30Bof silicon nitride (e.g., typically about 800 nanometers thick)deposited over the thermal oxide layer using a low-pressure chemicalvapor deposition (LPCVD) process at a temperature of about 850° C.

A first layer of an electrically conductive material (the firstelectrically conductive layer 40) is deposited over the first dielectriclayer 30. The first electrically conductive layer 40 is comprised of anelectrically conductive material such as, for example, polycrystallinesilicon (also termed polysilicon). In this regard, the firstelectrically conductive layer 40 is also referred to herein as the Poly0layer 40. The Poly0 layer 40 is typically about 300 nanometers thickwith subsequent polysilicon layers being thicker (e.g., typicallybetween about 1.0 and 2.5 microns thick). The Poly0 layer 40 (and otherpolysilicon layers described hereafter) may be deposited using a LPCVDprocess at a temperature of about 580° C. In depositing the Poly0 layer40 (and other polysilicon layers described hereafter), various dopantmaterials (e.g., phosphorous) can be employed to make the polysiliconelectrically conductive.

As is shown in FIGS. 1A and 2A, after the Poly0 layer 40 is deposited,the Poly0 layer 40 is patterned to provide a Poly0 bond pad area 42 thatis connected with one or more Poly0 interconnect lines 44. In thisregard, the Poly0 bond pad area 42 is rectangular, but it may bepatterned is any desirable shape (e.g., circular, triangular, hexagonal,etc.). The Poly0 interconnect lines 44 meet the Poly0 bond pad area 42at ends 44A thereof that abut the edge of the Poly0 bond pad area 42 andare shielded on either side thereof by Poly0 shield walls 46 extendingparallel with and laterally spaced away from the Poly0 interconnectlines 44. The Poly0 shield walls 46 terminate at ends 46A that areseparated by a small gap (e.g., one to a few microns) from theperipheral edge of the Poly0 bond pad area 42 so that the Poly0 shieldwalls 46 are electrically isolated from the Poly0 bond pad area 42. ThePoly0 bond pad area 42 and Poly0 interconnect lines 44 are electricallyisolated from the substrate 20 by the first dielectric layer 30, whereasthe Poly0 shield walls 46 extend vertically down through the firstdielectric layer 30 to contact the upper surface of the substrate 20.

After the Poly0 bond pad area 42 is formed in the Poly0 layer 40, asecond dielectric layer 50 is deposited over the Poly0 layer 40. Thesecond dielectric layer 50 is comprised of an electrically insulatingmaterial such as, for example, a sacrificial material (e.g., silicondioxide or silicate glass). In this regard, the second dielectric layer50 is also referred to herein as the Sacox1 layer 50. The Sacox1 layer50 (and other sacrificial layers described herein) may be depositedusing a LPCVD process at a temperature of about 580° C. The Sacox1 layer50 (and subsequent sacrificial layers) is typically about 2.0 micronsthick. Cuts 52 are then made in the Sacox1 layer 50. The cuts 52, aswith other features of the self-shadowed bond pad 10 wherein material isremoved from one or more layers of material, may be formed, for example,by a mask and etch removal process employing appropriate masking agentsand etchants depending upon the material that is to be removed. Each ofthe cuts 52 in the Sacox1 layer 50 is located within the perimeter ofthe Poly0 bond pad area 42 near the periphery of the Poly0 bond pad area42. The cuts 52 extend down through the Sacox1 layer 50 to expose theupper surface of the Poly0 bond pad area 42 in one or more locationsalong the length of each cut 52, and preferably along the entire lengthof each cut 52. At the same time, cuts 52 may be made through the Sacox1layer 50 over the Poly0 shield walls 46 to expose the upper surfaces ofthe Poly0 shield walls 46. FIGS. 1B and 2B show perspective and topviews after the cuts 52 have been made in the Sacox1 layer 50 to exposethe upper surfaces of the Poly0 bond pad area 40 and Poly0 shield walls46.

After the cuts 52 are made in the Sacox1 layer 50, a second layer ofelectrically conductive material (the second electrically conductivelayer 60) is deposited in the cuts 52 made in the Sacox1 layer. Thesecond electrically conductive layer 60 is comprised of an electricallyconductive material such as, for example, doped polysilicon. In thisregard, the second electrically conductive layer 60 is also referred toherein as the Poly1 layer 60. The Poly1 layer 60 fills the bottom andsidewalls of the cuts 52 in the Sacox1 layer 50 and covers the remainingportions of the Sacox1 layer 50.

A third layer of electrically conductive material (the thirdelectrically conductive layer 70) is then deposited over the Poly1 layer60. The third electrically conductive layer 70 is comprised of anelectrically conductive material such as, for example, dopedpolysilicon. In this regard, the third electrically conductive layer 70is also referred to herein as the Poly2 layer 70. Prior to depositingthe Poly2 layer 70 over the Poly1 layer 60, a third dielectric layer(not shown) of sacrificial material may have been deposited over thePoly1 layer 60 and removed from the regions of the Poly1 layer 60 ofinterest to the structures described herein. The third dielectric layer(the Sacox2 layer) may be utilized in maintaining desired separationbetween the Poly1 and Poly2 layers 60, 70 in othermicroelectromechanical structures, but such separation is not desiredherein. In this regard, the Poly1 and Poly2 layers 60, 70 may beconsidered to be a single layer of polysilicon material. The Poly2 layer70 typically fills in the remainder of the cuts 52 made in the Sacox1layer 50 to form, together with the Poly1 layer 60 material in the cuts52, Poly1/Poly2 shield walls 66 on top of the Poly0 shield walls 46 andPoly1/Poly2 support walls 68 on top of the Poly0 bond pad area 42. Thecuts 52 made in the Sacox1 layer 50 over the Poly0 shield walls 46 donot extend all the way to the cuts 52 made over the Poly0 bond pad area42 so that the ends 66A of the Poly1/Poly2 shield walls 66 are separatedby a small gap (e.g., one to a few microns) from the Poly1/Poly2 supportwalls 68 so that the Poly1/Poly2 shield walls 66 are electricallyisolated from the Poly1/Poly2 support walls 68. After the Poly2 layer 70is deposited, the combined Poly1 and Poly2 layers 60, 70 are patternedto provide a Poly1/Poly2 bond pad area 72 supported over the Poly0 bondpad area 42 by the Poly1/Poly2 support walls 68 and Poly1/Poly2 shields74 supported over the Poly0 interconnect lines 44 by the Poly0 andPoly1/Poly2 shield walls 46, 66. FIGS. 1C and 2C show perspective andtop views of the self-shadowed bond pad 10 after the Poly1 and Poly2layers 60, 70 have been patterned to provide the Poly1/Poly2 bond padarea 72 and Poly1/Poly2 shields 74.

The Poly1/Poly2 bond pad area 72 is electrically connected to andsupported above the Poly0 bond pad area 42 by the Poly1/Poly2 supportwalls 68. The portion of the Sacox1 layer 50 encircled by thePoly1/Poly2 support walls 68 may remain between the Poly0 andPoly1/Poly2 bond pad areas 42, 72 after subsequent etching steps toprovide further rigidity and support to the Poly1/Poly2 bond pad area72. If desired, etch release holes may be included in the polysiliconstructures described herein in order to allow for the removal ofisolated or encapsulated sacrificial material. The Poly1/Poly2 shields74 are typically electrically connected to the substrate 20 by the Poly0and Poly1/Poly2 shield walls 46, 66 on either side of the Poly0interconnect lines 44. The Poly1/Poly2 shields 74 terminate at ends 74Athat are separated by a small gap (e.g., one to a few microns) firom theperipheral edge of the Poly1/Poly2 bond pad area 72 so that thePoly1/Poly2 shields 74 are electrically isolated from the Poly1/Poly2bond pad area 72.

A fourth dielectric layer 80 is then deposited over the Poly2 layer 70.The fourth dielectric layer 80 is comprised of an electricallyinsulating material such as, for example, a sacrificial material (e.g.silicon dioxide or silicate glass). In this regard, the fourthdielectric layer 80 is also referred to herein as the Sacox3 layer 80.Cuts 82 are then made in the Sacox3 layer 80. Each of the cuts 82 in theSacox3 layer 80 is located within the perimeter of the Poly1/Poly2 bondpad area 72 near the periphery of the Poly1/Poly2 bond pad area 72. Thecuts 82 extend down through the Sacox3 layer 80 to expose the uppersurface of the Poly1/Poly2 bond pad area 72 in one or more locationsalong the length of each cut 82, and preferably along the entire lengthof each cut 82. FIGS. 1D and 2D show perspective and top views of theself-shadowed bond pad 10 after the cuts 82 have been made in the Sacox3layer 80.

After the cuts 82 are made in the Sacox3 layer 80, a fourth layer ofelectrically conductive material (the fourth electrically conductivelayer 90) is then deposited over the Sacox3 layer 80 filling in the cuts82 made in the Sacox3 layer 80 and covering the Sacox3 layer 80. Thefourth electrically conductive layer 90 is comprised of an electricallyconductive material such as, for example, doped polysilicon. In thisregard, the fourth electrically conductive layer 90 is also referred toherein as the Poly3 layer 90. After being deposited, the Poly3 layer 90is patterned to form a Poly3 bond pad area 92 overlying the Poly1/Poly2bond pad area 72. The Poly3 bond pad area 92 includes one or more Poly3tabs 94 extending outward from the periphery of the Poly3 bond bad area92. The Poly3 bond pad area 92 is electrically connected and supportedabove the Poly1/Poly2 bond pad area 72 by Poly3 support walls 98 foiledin the cuts 82 in the Sacox3 layer 80 upon deposition of the Poly3material. The portion of the Sacox3 layer 80 encircled by the Poly3support walls 98 may remain between the Poly1/Poly2 and Poly3 bond padareas 72, 92 after subsequent etching steps to provide further rigidityand support to the Poly3 bond pad area 92.

The Poly3 tabs 94 extend outward from the periphery of the Poly3 bondpad area 92 at locations coinciding with the points where the ends 44Aof the Poly0 interconnect lines 44 abut the Poly0 bond pad area 42. ThePoly3 tabs 94 are sufficiently sized in order to shadow the exposedportions of the Poly0 interconnect line 44 in the gap between thePoly1/Poly2 shield 74 and the Poly1/Poly2 bond pad area 72. Preferablythe Poly3 tabs 94 also shadow a small area around the exposed portionsof the Poly0 interconnect lines 44 as well. In this regard, the Poly3tabs 94 preferably overhang the ends 74A of the Poly1/Poly2 shields 74by at least 1 micron and preferably are wider than the Poly0interconnect line 44 by at least 1 micron on either side.

After the Poly3 layer 90 is patterned, an optional fifth dielectriclayer 100 may then deposited over the Poly3 layer 90. The fifthdielectric layer 100 is comprised of an electrically insulating materialsuch as, for example, a sacrificial material (e.g. silicon dioxide orsilicate glass). In this regard, the fifth dielectric layer 100 is alsoreferred to herein as the Sacox4 layer 100. Cuts 102 are then made inthe Sacox4 layer 100. Each of 30 the cuts 102 in the Sacox4 layer 100 islocated within the perimeter of the Poly3 bond pad area 92, and as isillustrated, may be near the periphery of the Poly3 bond pad area 92.The cuts 102 extend down through the Sacox4 layer 100 to expose theupper surface of the Poly3 bond pad area 102 in one or more locationsalong the length of each cut 102, and preferably along the entire lengthof each cut 102. In addition to the cuts 102, holes 104 may also beformed in the Sacox4 layer 100. The holes 104 are located over the Poly3tabs 94. FIGS. 1F and 2F show perspective and top views of theself-shadowed bond pad 10 after the cuts 102 and holes 104 have beenmade in the Sacox4 layer 100.

An optional fifth layer of electrically conductive material (the fifthelectrically conductive layer 110) may then deposited over the Sacox4layer 100 filling in the cuts 102 made in the Sacox4 layer 100 andcovering the Sacox4 layer 100. The fifth electrically conductive layer110 is comprised of an electrically conductive material such as, forexample, doped polysilicon. In this regard, the fifth electricallyconductive layer 110 is also referred to herein as the Poly4 layer 110.After being deposited, the Poly4 layer 110 is patterned to form a Poly4bond pad area 112 overlying the Poly3 bond pad area 92. The Poly4 bondpad area 112 may include one or more Poly4 tabs 114 extending outwardfrom the periphery of the Poly4 bond bad area 112. The Poly4 bond padarea 112 is electrically connected and supported above the Poly3 bondpad area 92 by Poly4 support walls 118 formed in the cuts 102 in theSacox4 layer 100 upon deposition of the Poly4 material. The portion ofthe Sacox4 layer 100 encircled by the Poly4 support walls 118 may remainbetween the Poly3 and Poly4 bond pad areas 92, 112 after subsequentetching steps to provide further rigidity and support to the Poly4 bondpad area 112.

The Poly4 tabs 114 extend outward from the periphery of the Poly4 bondpad area 112 in appropriate locations so that the Poly4 tabs 114 overlythe Poly3 tabs 94. As is illustrated, the Poly4 tabs 114 may be slightlysmaller or larger in area than the Poly3 tabs 94. The Poly4 tabs 114help shadow the exposed portions of the Poly0 interconnect line 44 inthe gap between the Poly1/Poly2 shield 74 and the Poly1/Poly2 bond padarea 72. The Poly4 tabs 114 may also be anchored to the Poly3 tabs 94 byanchor posts 120 comprised of Poly4 material that fills the holes 104formed in the Sacox4 layer 100 above the Poly3 tabs 94. Anchoring thePoly4 tabs 114 to the Poly3 tabs 94 enhances vertical rigidity of thetabs 94, 114 thus reducing out of plane curvature due to metalization.This minimizes the possibility of inadvertent contact and breaking ofthe tabs 94, 114 during subsequent probing and/or bonding to the pad.FIGS. 1G and 2G show perspective and top views of the self-shadowed bondpad 10 after the Poly4 layer 110 has been deposited and patterned. FIG.3 shows a cross-sectional view of the self-shadowed bond pad 10 takenalong line A--A in FIG. 1G.

After the Poly4 bond pad area and tabs 112, 114 are patterned from thePoly4 layer 110, the Poly4 bond pad area 112 may be metalized inpreparation for attaching electrical leads and the like thereto forconnecting the MEMS device to off chip components or contacting the bondpad with probe leads or the like for testing purposes. In this regard, ablanket metalization process may be employed because the shadowingprovided by the Poly 3 and Poly4 tabs 94, 114 prevents the gold or othermaterial from shorting the Poly0 interconnect lines 44 to the Poly0 andPoly1/Poly2 shield walls 46,66 and the Poly1/Poly2 shields 74 where thePoly0 interconnect lines 44 are exposed. Additionally, the Poly3 andPoly4 tabs 94, 114 may also help reduce the possibility that looseparticles on the surface of the chip might later contact the exposedPoly0 interconnect line 44 causing an undesirable short circuitcondition with the Poly0 and Poly1/Poly2 shield walls 46,66 or thePoly1/Poly2 shields 74.

Although not illustrated, it should be noted that instead of havingPoly3 and/or Poly4 tabs 94, 114 positioned at locations coinciding withthe locations where the Poly0 interconnect lines 44 abut the Poly0 bondpad area 42, it is also possible to pattern the Poly3 and/or Poly4 bondpad areas 92, 112 to have cantilevered edges that extend outward alongthe entire length of one or more of the edges of the Poly3 and/or Poly4bond pad areas 92, 112 to shadow one or more Poly0 interconnect lines44. However, Poly3 and/or Poly4 tabs 94, 114 are preferred since theirsmaller area makes them less likely to be damaged when attaching probeleads or the like to the bond pad 10.

Although other microfabrication processes may be employed in fabricatingthe self-shadowed bond pad 10 as described above, the SUMMiT V™ surfacemicromachining process developed at Sandia National Laboratories anddescribed, for example, in U.S. Pat. No. 6,082,208, issued Jul. 4, 2000entitled “Method For Fabricating Five-Level MicroelectromechanicalStructures And Microelectromechanical Transmission Formed”, incorporatedby reference herein, is particularly useful for fabricating theself-shadowed bond pad 10. Employing the SUMMiT V™ surfacemicromachining process to fabricate the self-shadowed bond pad 10permits easy incorporation of the self-shadowed bond pad 10 into MEMsystems fabricated from five polysilicon levels such as some MEM mirrorpositioning systems useful in optical cross connects and the like.

Referring now to FIGS. 4-5, the concept of shadowing the exposed lowerlevel polysilicon interconnect lines 44 with tabs or the like extendingfrom the upper level polysilicon layers does not require a pair ofoverlying tabs that are anchored together nor do the tabs have to extendonly from the bond pad areas. FIG. 4 illustrates a bond pad structure210 wherein the Poly3 bond pad area 92 does not have any tab portionsand only the Poly4 bond pad area 112 includes one or more tab portions114 extending outward from the peripheral edges of the Poly4 bond padarea 112 that shadow the exposed Poly0 interconnect lines 44 in the gapbetween the Poly1/Poly2 shield 74 and the Poly1/Poly2 bond pad area 72.It is also possible to pattern the Poly4 bond pad area 112 without anytab portions and only have tab portions 94 extending outward from thePoly3 bond pad area 92.

By way of further example, the tab that shadows the desired area on thesubstrate need not be supported from the bond pad structure 10. FIG. 5illustrates an exemplary self-shadowed bond pad structure 310 whereinthe Poly3 tab 94 is supported from a Poly3 post 312 extending upwardfrom the Poly1/Poly2 shield 72 rather than extending outward from thePoly3 bond pad area 92. The Poly3 tab 94 extends past the end 74A of thePoly1/Poly2 shield 74 to overhang and thereby shadow the exposed Poly0interconnect line 44 in the gap between the Poly1/Poly2 shield 74 andthe Poly1/Poly2 bond pad area 72. As is shown in FIG. 5, the Poly3 bondpad area 92 (and also possibly the Poly4 bond pad area 112) may need tobe staggered back from the perimeter of the Poly1/Poly2 bond pad area 72in a tiered fashion in order to allow the Poly3 tab 94 to extendslightly over the edge of the Poly1/Poly2 bond pad area 72 withoutcontacting the Poly3 bond pad area 92 causing a short circuit condition.

Referring now FIGS. 6A-C, the concept of shadowing exposed lower levelpolysilicon structures with tabs, cantilevered edges or the likeextending from upper level polysilicon structures is not restricted toonly bond pad structures. By way of example, FIG. 6A shows a perspectiveview of one embodiment of a positionable MEM mirror 410 that is held inplace during various processing steps by thin polysilicon filaments 420(e.g., fuses) extending from polysilicon bond pads 430 arranged in pairsaround the periphery of the MEM mirror 410. FIG. 6B shows an enlargedperspective view of two of the filaments 420. The filaments 420 aresevered (e.g., burned by sending sufficient electrical currenttherethrough) prior to positioning the MEM mirror 410 in a desiredorientation by lifting and/or tilting it about one or more axes. In thisregard, it is desirable that the filaments 420 not become metalized whenthe surface of the MEM mirror 410 is metalized (e.g., with gold) toenhance its reflectivity since metalized filaments will have differentelectrical characteristics. Due to their proximity to the periphery ofthe MEM mirror 410, it is quite possible that some of the filaments 420may become metalized even if a shadow mask is employed when metalizingthe surface of the MEM mirror 410. For example, if the mask is slightlyoffset in one direction, some of the filaments 410 may be metalizedwhile other filaments 420 are not metalized making the optimalelectrical signal required to sever the metalized filaments 420different from that required to sever the non-metalized filaments 420,possibly resulting in reduced yields on automated testing equipment.

FIG. 6C shows one manner of reducing or eliminating possiblemetalization of the filaments 420 holding MEM mirror 410 in place. Inthe embodiment of FIG. 6C, the upper polysilicon layer of the MEM mirror410 is patterned to include a tab portion 414 that extends outward fromthe periphery of the MEM mirror 410 in order to shadow an area on thesubstrate 20 encompassing the filaments 420. It is not required that thetab portion 414 be attached to the moveable structure (i.e., the MEMmirror 410). For example, one of the bond pads 430 could include anotherupper level layer of polysilicon that includes a tab overhanging thefilaments 420 similar to the previously described bond pad structures.However, having the tab portion 414 attached to the MEM mirror 410 maybe preferable since portions of the severed filaments 420 that remainattached to the MEM mirror 410 will not come into contact with the tabportion 420 when the MEM mirror 410 is lifted and/or tilted therebypossibly restricting or altering the movement of the MEM mirror 410.

Referring now FIG. 7A, there is shown a perspective view of a portion ofone embodiment of a positionable MEM mirror 510 that includes one ormore non-shadowed compliant (i.e., spring-like) members 540 that extendoutward from the edge of the mirror 510. The compliant member 540 may beutilized to connect the mirror 510 to an actuator arm (not shown) or thelike that is used (possibly in conjunction with other actuator armsconnected to the mirror 510 by other compliant members 540) to positionthe mirror 510 in a desired orientation with respect to the substrate20. In this regard, the compliant member 540 transmits force from theactuator arm to the mirror 510 while allowing the mirror 510 andactuator arm to move through different radius arcs. Thus, it isgenerally imperative that the compliant member 540 remain non-metalized,as metalization may induce severe curvature of the compliant member andalso undesirable fatigue properties. As with filaments (not shown)temporarily holding the mirror 510 in place, due to its proximity to theperiphery of the MEM mirror 510. it is quite possible that the compliantmember 540 may become metalized even if a shadow mask is employed whenmetalizing the surface of the MEM mirror 510.

FIG. 7B shows one manner of reducing or eliminating possiblemetalization of the compliant member 540. In the embodiment of FIG. 7B,the upper polysilicon layer of the MEM mirror 510 is patterned toinclude a tab portion 518 that extends outward from the periphery of theMEM mirror 510 in order to shadow an area on the substrate 20encompassing the compliant member 540. The MEM mirror 510 also includesa tab portion 514 that shadows one or more filaments 520 temporarilyholding the MEM mirror 510 in place until severed as per the embodimentshown in FIG. 6C. Since the compliant member 540 is typically largerthan the filaments 520 temporarily holding the MEM mirror 510 in place,tab portion 518 is typically larger than tab portion 514. However, therelatively large tab portion 518 over the compliant member 540 is notexpected to cause problems such as undesired contact with the compliantmember 540 or actuator arm 550 during operation. This is because uponmetalization, the tab portion 518 (as well as tab portion 514) shouldcurl up due to the presence of metal on top of the relatively non-rigidpolysilicon tab portions 514, 518.

While various embodiments of the present invention have been describedin detail, further modifications and adaptations of the invention mayoccur to those skilled in the art. However, it is to be expresslyunderstood that such modifications and adaptations are within the spiritand scope of the present invention.

1-11. (canceled)
 12. A method for self-shadowing a portion of amicroelectromechanical structure fabricated on a substrate fromundesired metalization during a metalization fabrication process step,said method comprising the steps of: depositing a lower layer ofmaterial on the substrate; patterning a lower structure from the lowerlayer of material; depositing an upper layer of material on thesubstrate; patterning an upper structure from the upper layer ofmaterial, wherein the upper structure is patterned to include alaterally extending portion thereof that extends laterally from theupper structure to shadow an area on the substrate including a portionof the lower structure that is to remain non-metalized.
 13. The methodof claim 12 wherein in said patterning steps, the lower layer ofmaterial is patterned to provide an interconnect line and the upperlayer is patterned to provide a bond pad area.
 14. The method of claim13 wherein in said step of patterning the upper layer, the upper layeris patterned to provide a tab extending laterally from an edge of thebond pad area.
 15. The method of claim 13 wherein in said step ofpatterning the upper layer, the upper layer is patterned to provide thebond pad area with a cantilevered edge.
 16. The method of claim 12wherein in said patterning steps, the lower layer is patterned toprovide an interconnect line and the upper layer is patterned to providea tab extending laterally from a post extending upward from a shieldstructure overlying the interconnect line.
 17. The method of claim 12wherein in said patterning steps, the upper layer is patterned toprovide a positionable mirror and the lower layer is patterned toprovide at least one filament for holding the mirror in place until thefilament is severed.
 18. The method of claim 12 wherein in saidpatterning steps, the upper layer is patterned to provide a positionablemirror and the lower layer is patterned to provide at least onecompliant member extending outward from an edge of the mirror.
 19. Themethod of claims 17 wherein in said step of patterning the upper layer,the upper layer is patterned to provide a tab extending laterally froman edge of the mirror.
 20. The method claims 17 wherein in said step ofpatterning the upper layer, the upper layer is patterned to provide themirror with a cantilevered edge.
 21. The method of claim 12 wherein insaid depositing steps, at least one of the lower layer of material andthe upper layer of material comprises an electrically conductivematerial.
 22. The method of claim 21 wherein in said depositing steps,the substrate comprises silicon and the electrically conductive materialcomprises doped polysilicon.
 23. The method of claim 12 furthercomprising the step of depositing at least a layer of sacrificialmaterial between the lower and upper layers of material. 24-42.(canceled)
 43. The method of claim 18 wherein in said step of patterningthe upper layer, the upper layer is patterned to provide a tab extendinglaterally from an edge of the mirror.
 44. The method claim 18 wherein insaid step of patterning the upper layer, the upper layer is patterned toprovide the mirror with a cantilevered edge.